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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56651/D Rev 0, 6/98 Advance Information INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC DSP56651 Motorola designed the RAM-based DSP56651 emulation device to support the rigorous demands of developing applications for the cellular subscriber market. The high level of on-chip integration in the DSP56651 and its volume production companion device DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance. The DSP56651 chip combines the power of Motorola's 32-bit M*CORE TM MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band processor. Figure 1 shows the basic block diagram of the DSP56651. Timer/ PWM External Memory RAM 512 x 32 ROM 4K x 32 Clocks DSP PLL MCU OnCE DSP OnCE Watch Dog Program Interrupt Timer Edge I/O Smart Card I/F Keypad I/F Queued SPI M*CORE MicroRISC Core MCU - DSP INTERFACE 1K x 16 RAM MESSAGING UNIT UART MUX Serial Audio CODEC I/F AA1617 JTAG X Data RAM (7+1)K x 16 Y Data RAM 8K x 16 Program RAM 24K x 24 X Data ROM 9K x 16 Y Data ROM 9K x 16 Program ROM 24K x 24 56600 DSP Core Serial Audio CODEC I/F Baseband CODEC I/F Figure 1-1 DSP56651 System Block Diagram Development Part Only--Not intended for production. Requires a higher voltage than the production part This document contains information on a new product. Specifications and information herein are subject to change without notice. Preliminary (c)1998 MOTOROLA, INC. JTAG DSP56651 Protocol Timer DSP56652 TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 PIN AND SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: 1 (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low; for example, the RESET pin is active when low Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Preliminary ii DSP56652 Technical Data Sheet MOTOROLA DSP56651 Features FEATURES RISC M*CORE MCU * * * * * * * * * 32-bit load/store RISC architecture Fixed 16-bit instruction length 16-entry 32-bit general-purpose register file 32-bit internal address and data buses Efficient four-stage, fully interlocked execution pipeline Single-cycle execution for most instructions, two cycles for branches and memory accesses Special branch, byte, and bit manipulation instructions Support for byte, half-word, and word memory accesses Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file High Performance DSP56600 Core * * * * * * * * * * 1 x engine (e.g., 70 MHz = 70 MIPS) Fully pipelined 16 x 16-bit parallel multiplier-accumulator (MAC) Two 40-bit accumulators including extension bits 40-bit parallel barrel shifter Highly parallel instruction set with unique DSP addressing modes Position-independent code support Nested hardware DO loops Fast auto-return interrupts On-chip support for software patching and enhancements Realtime trace capability via address bus visibility mode Preliminary MOTOROLA DSP56651 Technical Data Sheet iii DSP56651 Features On-chip Memories * * * * * * 4K x 32-bit MCU ROM 512 x 32-bit MCU RAM 24K x 24-bit DSP program ROM 24K x 24-bit DSP program RAM 18K x 16-bit DSP data ROM, split into 9K x 16-bit X and 9K x 16 Y data ROM spaces 16K x 16-bit DSP data RAM, split into (7+1)K x 16-bit X and 8K x 16-bit Y data RAM spaces On-chip Peripherals * * * * * * * * * * * * * * * * * Fully programmable phase-locked loop (PLL) for DSP clock generation External interface module (EIM) for glueless system integration External 22-bit address and 16-bit data MCU buses Thirty-two source MCU interrupt controller Intelligent MCU/DSP interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control Serial audio codec port Serial baseband codec port Protocol timer frees the MCU from radio channel timing events Queued serial peripheral interface (SPI) Keypad port capable of scanning up to an 8 x 8 matrix keypad General-purpose MCU and DSP timers Pulse width modulation output Universal asynchronous receiver/transmitter (UART) with FIFO IEEE 1149.1-compliant boundary scan JTAG test access port (TAP) Integrated DSP/M*CORE On-Chip Emulation (OnCETM) module DSP address bus visibility mode for system development ISO 7816-compatible Smart Card port Preliminary iv DSP56651 Technical Data Sheet MOTOROLA DSP56651 Target Applications Operating Features: * * * * * Comprehensive static and dynamic power management M*CORE operating frequency: dc to 16.8 MHz at 2.4 V DSP operating frequency: dc to 58.8 MHz at 2.4 V Operating temperature: -40 to 85C ambient Package option: 17 x 17 mm, 196-lead PBGA TARGET APPLICATIONS The DSP56651 is intended for the development of cellular subscriber applications and other applications needing both DSP and control processing. PRODUCT DOCUMENTATION The four manuals listed in Table 1 are required for a complete description of the DSP56651 and are necessary to design with the part properly. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or the World Wide Web. Table 1 DSP56651 Documentation Document Name DSP56600 Family Manual M*CORE Reference Manual DSP56652 User's Manual DSP56651 Technical Data Description of Contents Order Number Detailed description of the DSP56600 family core processor DSP56600FM/AD architecture and instruction set Detailed description of the M*CORE MCU and instruction MCORERM/AD set Detailed description of DSP56652 memory, peripherals, and interfaces, much of which are common to the DSP56651 DSP56651 pin and package descriptions; electrical and timing specifications DSP56652UM/AD DSP56651/D Preliminary MOTOROLA DSP56651 Technical Data Sheet v DSP56651 Product Documentation Preliminary vi DSP56651 Technical Data Sheet MOTOROLA SECTION 1 PIN AND SIGNAL DESCRIPTIONS INTRODUCTION The pins and signals of the DSP56651 are described in the following sections. Figure 1-1 and Figure 1-2 on page 1-3 are top and bottom views of the package, respectively, showing the pin-outs. Subsequent tables list the pins by number and signal name. Figure 1-3 on page 1-11 is a representational pin-out of the chip grouping the signals by their function. Subsequent tables identify the signals of each group. DSP56651 PIN DESCRIPTION The following section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals of the DSP56651 are allocated for the 196-pin plastic ball grid array (PBGA) package. Top and bottom views of the PBGA package are shown in Figure 1-1 and Figure 1-2 on page 1-3 with their pin-outs. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-1 Pin and Signal Descriptions DSP56651 Pin Description PBGA Package Description Top View 1 A NC 2 A20 3 TOUT0 4 TOUT3 5 TOUT6 6 SPICS4 7 GNDH 8 VCCHQ 9 DSP_IRQ 10 SRDB 11 GNDE 12 SRDA 13 STDA 14 NC B GNDA A18 A21 TOUT2 TOUT7 SPICS1 VCCQ MOSI SC2B SC0A SCKA PSTAT2 PSTAT1 GNDK C VCCA A17 A19 TOUT1 TOUT5 VCCH GNDQ SCKB STDB SC1A PSTAT3 VCCK PSTAT0 SIZ1 D A13 A15 A16 A14 TOUT4 SPICS3 SCK MISO SC1B SC2A VCCE SIZ0 MUX_CTL CTS E A8 A12 A11 A10 GND SPICS2 SPICS0 NC SC0B GND RTS RX TEST TX F VCCA A7 A9 A6 A5 GND GND GND GND TDO TCK DSP_DE TDI TRST G A0 GNDA A4 A3 A2 GND GND GND GND MCU_DE ROW7 VCCHQ ROW6 TMS H CKIH EB1 J GNDF VCCQ DSP56651 A1 EB0 CKIL GND GND GND GND GNDG VCCG VCCQ ROW4 ROW5 VCCHQ CKOH GNDQ GND GND GND GND GNDQ ROW2 INT7 ROW1 ROW3 K CKO VCCF OE R/W GND D12 PWR_EN GNDB VCCP GND INT6 INT5 INT4 ROW0 L CS0 CS1 VCCC D5 GNDD D11 SIMCLK VCCB PCAP SIM DATA SIM RESET RESET_ IN VCCG INT0 GNDG INT3 M GNDC CS2 CS4 D1 VCCD D8 D13 VCCQ RESET_ OUT COL1 COL5 COL7 INT2 N CS3 CS5 D0 D4 D7 D10 D15 GNDQ GNDP1 COL0 COL3 COL6 INT1 P NC D2 D3 D6 D9 D14 VCCHQ SENSE GNDP MOD STO COL2 COL4 NC AA1694 Figure 1-1 DSP56651 Plastic Ball Grid Array (PBGA), Top View Preliminary 1-2 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Pin Description Bottom View 14 NC 13 STDA 12 SRDA 11 GNDE 10 SRDB 9 DSP_IRQ 8 VCCHQ 7 GNDH 6 SPICS4 5 TOUT6 4 TOUT3 3 TOUT0 2 A20 1 NC A GNDK PSTAT1 PSTAT2 SCKA SC0A SC2B MOSI VCCQ SPICS1 TOUT7 TOUT2 A21 A18 GNDA B SIZ1 PSTAT0 VCCK PSTAT3 SC1A STDB SCKB GNDQ VCCH TOUT5 TOUT1 A19 A17 VCCA C CTS MUX_CTL SIZ0 VCCE SC2A SC1B MISO SCK SPICS3 TOUT4 A14 A16 A15 A13 D TxD TEST RxD RTS GND SC0B NC SPICS0 SPICS2 GND A10 A11 A12 A8 E TRST TDI DSP_DE TCK TDO GND GND GND GND A5 A6 A9 A7 VCCA F TMS ROW6 VCCHQ ROW7 MCU_DE GND GND GND GND A2 A3 A4 GNDA A0 G ROW5 ROW4 VCCQ VCCG GNDG GND GND GND GND CKIL EB0 A1 EB1 CKIH H ROW3 ROW1 INT7 ROW2 GNDQ GND GND GND GND GNDQ CKOH VCCHQ VCCQ GNDF J ROW0 INT4 INT5 INT6 GND VCCP GNDB PWR_EN D12 GND R/W OE VCCF CKO K INT3 GNDG INT0 VCCG RESET_ IN PCAP SIM DATA SIM VCCB SIMCLK D11 GNDD D5 VCCC CS1 CS0 L INT2 COL7 COL5 COL1 RESET_ OUT VCCQ D13 D8 VCCD D1 CS4 CS2 GNDC M INT1 COL6 COL3 COL0 GNDP1 RESET GNDQ D15 D10 D7 D4 D0 CS5 CS3 N NC COL4 COL2 STO MOD GNDP SENSE VCCHQ D14 D9 D6 D3 D2 NC P AA1695 Figure 1-2 DSP56651 Plastic Ball Grid Array (PBGA), Bottom View Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-3 Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Signal Name Not Connected (NC), reserved A20 TOUT0 TOUT3 TOUT6 SPICS4 GNDH VCCHQ DSP_IRQ SRDB GNDE SRDA STDA NC GNDA A18 A21 TOUT2 TOUT7 SPICS1 VCCQ MOSI SC2B SC0A SCKA Pin No. B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 Signal Name PSTAT2 PSTAT1 GNDK VCCA A17 A19 TOUT1 TOUT5 VCCH GNDQ SCKB STDB SC1A PSTAT3 VCCK PSTAT0 SIZ1 A13 A15 A16 A14 TOUT4 SPICS3 SCK MISO Pin No. D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 SC1B SC2A VCCE SIZ0 MUX_CTL CTS A8 A12 A11 A10 GND SPICS2 SPICS0 NC SC0B GND RTS RxD TEST TxD VCCA A7 A9 A6 A5 Signal Name Preliminary 1-4 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued) Pin No. F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 GND GND GND GND TDO TCK DSP_DE TDI TRST A0 GNDA A4 A3 A2 GND GND GND GND MCU_DE ROW7 VCCHQ ROW6 TMS CKIH EB1 Signal Name Pin No. H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 A1 EB0 CKIL GND GND GND GND GNDG VCCG VCCQ ROW4 ROW5 GNDF VCCQ VCCHQ CKOH GNDQ GND GND GND GND GNDQ ROW2 INT7 ROW1 Signal Name Pin No. J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 ROW3 CKO VCCF OE R/W GND D12 PWR_EN GNDB VCCP GND INT6 INT5 INT4 ROW0 CS0 CS1 VCCC D5 GNDD D11 SIMCLK VCCB PCAP RESET_IN Signal Name Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-5 Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued) Pin No. L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 VCCG INT0 GNDG INT3 GNDC CS2 CS4 D1 VCCD D8 D13 VCCQ SIMDATA RESET_OUT COL1 COL5 Signal Name Pin No. M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 COL7 INT2 CS3 CS5 D0 D4 D7 D10 D15 GNDQ SIMRESET GNDP1 COL0 COL3 COL6 INT1 Signal Name Pin No. P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 NC D2 D3 D6 D9 D14 VCCHQ SENSE GNDP MOD STO COL2 COL4 NC Signal Name Preliminary 1-6 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Pin Description Table 1-2 DSP56651 PBGA Signal Identification by Name Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 CKIH CKIL CKO Pin No. G1 H3 G5 G4 G3 F5 F4 F2 E1 F3 E4 E3 E2 D1 D4 D2 D3 C2 B2 C3 A2 B3 H1 H5 K1 Signal Name CKOH COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 CS0 CS1 CS2 CS3 CS4 CS5 CTS D0 D1 D2 D3 D4 D5 D6 D7 D8 Pin No. J4 N11 M11 P12 N12 P13 M12 N13 M13 L1 L2 M2 N1 M3 N2 D14 N3 M4 P2 P3 N4 L4 P4 N5 M6 Signal Name D9 D10 D11 D12 D13 D14 D15 DSP_DE DSP_IRQ EB0 EB1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin No. P5 N6 L6 K6 M7 P6 N7 F12 A9 H4 H2 E10 E5 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-7 Pin and Signal Descriptions DSP56651 Pin Description Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued) Signal Name GND GND GND GND GND GND GNDA GNDA GNDB GNDC GNDD GNDE GNDF GNDG GNDG GNDH GNDK GNDP GNDP1 GNDQ GNDQ GNDQ GNDQ INT0 INT1 Pin No. J6 J7 J8 J9 K10 K5 B1 G2 K8 M1 L5 A11 J1 H10 L13 A7 B14 P9 N10 C7 J10 J5 N8 L12 N14 Signal Name INT2 INT3 INT4 INT5 INT6 INT7 MCU_DE MISO MOD MOSI MUX_CTL NC NC NC NC NC OE PCAP PSTAT0 PSTAT1 PSTAT2 PSTAT3 PWR_EN R/W RESET_IN Pin No. M14 L14 K13 K12 K11 J12 G10 D8 P10 B8 D13 A1 A14 E8 P1 P14 K3 L9 C13 B13 B12 C11 K7 K4 L10 Signal Name RESET_OUT ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 RTS RxD SC0A SC0B SC1A SC1B SC2A SC2B SCK SCKA SCKB SENSE SIMCLK SIMDATA SIMRESET SIZ0 Pin No. M10 K14 J13 J11 J14 H13 H14 G13 G11 E11 E12 B10 E9 C10 D9 D10 B9 D7 B11 C8 P8 L7 M9 N9 D12 Preliminary 1-8 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Pin Description Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued) Signal Name SIZ1 SPICS0 SPICS1 SPICS2 SPICS3 SPICS4 SRDA SRDB STDA STDB STO TCK TDI TDO TEST TMS Pin No. C14 E7 B6 E6 D6 A6 A12 A10 A13 C9 P11 F11 F13 F10 E13 G14 Signal Name TOUT0 TOUT1 TOUT2 TOUT3 TOUT4 TOUT5 TOUT6 TOUT7 TRST TxD VCCA VCCA VCCB VCCC VCCD VCCE Pin No. A3 C4 B4 A4 D5 C5 A5 B5 F14 E14 C1 F1 L8 L3 M5 D11 Signal Name VCCF VCCG VCCG VCCH VCCHQ VCCHQ VCCHQ VCCHQ VCCK VCCP VCCQ VCCQ VCCQ VCCQ Pin No. K2 H11 L11 C6 A8 G12 J3 P7 C12 K9 B7 J2 H12 M8 Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-9 Pin and Signal Descriptions DSP56651 Signal Description DSP56651 SIGNAL DESCRIPTION DSP56651 signals are organized into nineteen functional groups as summarized in Table 1-3. Figure 1-3 is a diagram of DSP56651 signals by functional group. Table 1-3 Signal Functional Group Allocations Functional Group Power (VCCX) Ground (GNDX) Substrate ground (GND) PLL and clocks Address bus Data bus Bus control Chip selects Reset, mode, and multiplexer control External interrupts Timers Keypad port Serial data port (UART) Serial control port (QSPI) Smart Card port (SIM) Serial audio codec port (SAP) Baseband codec port Emulation port Debug control port JTAG test access port (TAP) Development and Test External Interface Module (EIM) Number of Signals 20 17 20 5 22 16 4 6 5 9 8 16 4 8 5 6 6 6 2 6 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14 Table 1-15 Table 1-16 Table 1-17 Table 1-18 Table 1-19 Table 1-20 Table 1-21 Table 1-22 Detailed Description Table 1-4 Table 1-5 Preliminary 1-10 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description DSP56651 VCCA VCCB VCCC VCCD VCCE VCCF VCCG VCCH VCCHQ VCCK VCCP VCCQ GNDA GNDB GNDC GNDD GNDE GNDF GNDG GNDH GNDK GNDP GNDP1 GNDQ GND CKIH CKIL CKO CKOH PCAP A0-A21 D0-D15 R/W EB0 EB1 OE Chip Selects RESET_IN RESET_OUT MOD MUX_CTL STO 2 6 2 4 4 2 Power Inputs: Address Bus Smart Card Bus Control Data Bus Audio Codec Clock Output GPIO/Keypad/Int/JTAG/UART/STO Baseband Codec/Timers/QSPI Quiet Power High Emulation Port PLL Internal Logic (Quiet) Grounds: Address Bus Smart Card Bus Control Data Bus Audio Codec Clock Output GPIO/Keypad/Int/JTAG Baseband Codec/Timers Emulation Port PLL PLL Internal Logic (Quiet) Substrate Ground PLL and Clocks Interrupts INT0-INT5 INT6/STDA/DSR or TRST INT7/SRDA/DTR/SCK or TMS DSP_IRQ TOUT0-TOUT7 COL0-COL5 COL6/OC1 COL7/PWM ROW0-ROW4 ROW5/IC2B ROW6/SC2A/DCD or DSP_DE ROW7/SCKA/RI or TCK TxD or TDO RxD/IC1 or TDI RTS/IC2 or RESET_IN CTS or MCU_DE Timers 8 6 Keypad Port 5 Serial Data Port (UART) Queued Serial Port Smart Card Port 5 2 SPICS0-SPICS4 SCK MISO MOSI SIMCLK SENSE SIMDATA SIMRESET PWR_EN STDA SRDA SCKA SC0A-SC2A STDB SRDB SCKB SC0B-SC2B SIZ0-SIZ1 PSTAT0-PSTAT3 MCU_DE DSP_DE TCK TDI TDO TMS TRST TEST 4 20 Serial Audio Codec Port 3 22 16 External Address Bus External Data Bus External Bus Control Baseband Codec Port 3 2 4 Emulation Port Debug Control Port JTAG Port 4 CS0 CS1-CS4 CS5 Reset, Mode, and Multiplexer Control AA1690 Figure 1-3 Signals Identified by Functional Group Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-11 Pin and Signal Descriptions DSP56651 Signal Description Power Table 1-4 Power Power Names VCCA VCCB VCCC VCCD VCCE VCCF Description Address Bus power--These lines supply power to the address bus. Smart Card interface power--This line supplies isolated power for Smart Card Interface I/O drivers. Bus control power--This line supplies power to the bus control logic. Data bus power--These lines supply power to the data bus. Audio codec port power--This line supplies power to audio codec I/O drivers. Clock output power--This line supplies a quiet power source for the CKOUT output. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCF line and the GNDF line. GPIO power--This line supplies power to the GPIO, keypad, data port, interrupts, STO, and JTAG I/O drivers. Baseband codec and timer power--This line supplies power to the baseband codec, timer and QSPI I/O drivers. Quiet power high--These lines supply a quiet power source to the pre-driver voltage converters. This value should be greater than or equal to the maximum value of the power supplies of the chip I/O drivers (i.e., the maximum of VCCA, VCCB, VCCC, VCCD, VCCE, VCCF, VCCG, VCCH, and VCCK). Emulation port power--This line supplies power to the emulation port I/O drivers. Analog PLL circuit power--This line is dedicated to the analog PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP and GND P1 lines. Quiet power--These lines supply a quiet power source to the internal logic circuits. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ lines and the GNDQ lines. VCCG VCCH VCCHQ VCCK VCCP VCCQ Preliminary 1-12 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Ground Table 1-5 Ground Ground Names GNDA GNDB GNDC GNDD GNDE GNDF Description Address Bus ground--These lines connect system ground to the address bus. Smart Card interface ground--These lines connect system ground to the Smart Card bus. Bus control ground--This line connects ground to the bus control logic. Data bus ground--These lines connect system ground to the data bus. Audio codec port ground--These lines connect system ground to the audio codec port. Clock output ground--This line supplies a quiet ground connection for the clock output drivers. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCF line and the GNDF line. GPIO ground--These lines connect system ground to GPIO, keypad, data port, interrupts, STO, and JTAG I/O drivers. Baseband codec and timer ground--These lines connect system ground to the baseband codec, timer and QSPI I/O drivers. Emulation port ground--These lines connect system ground to the emulation port I/O drivers. Analog PLL circuit ground--This line supplies a dedicated quiet ground connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. Analog PLL circuit ground--This line supplies a dedicated quiet ground connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. Quiet ground--These lines supply a quiet ground connection for the internal logic circuits. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ line and the GNDQ line. Substrate ground--These lines must be tied to ground. GNDG GNDH GNDK GNDP GNDP1 GNDQ GND Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-13 Pin and Signal Descriptions DSP56651 Signal Description PLL and Clock Table 1-6 PLL and Clock Signals Signal Name CKIH Signal Type Input State during Reset Input Signal Description High frequency clock input--This signal provides the high frequency input clock. This clock may be other a CMOS square wave or sinusoid input. Low frequency clock input--This signal provides the low frequency input clock and should be less than or equal to the frequency of CKIH. This is the default input clock after reset. DSP/MCU output clock--This signal provides an output clock synchronized to the DSP or MCU core internal clock phases, according the selected programming option. The choices of clock source and enabling/disabling the output signal are software selectable. High frequency clock output--This signal provides an output clock derived from the CKIH input. This signal can be enabled or disabled by software. PLL capacitor--This signal is used to connect the required external filter capacitor to the PLL filter. Connect one end of the capacitor to PCAP and the other to VCCP. The value of the capacitor is specified in Section 2 of this data sheet. CKIL Input Input CKO Output Driven low CKOH Output Driven low Indeterminate PCAP Input/ Output Address Bus Table 1-7 Address Bus Signals Signal Names A0-A21 Signal Type Output State during Reset Driven low Signal Description Address bus--These signals specify the address for external memory accesses. If there is no external bus activity, A0-A21 remain at their previous values to reduce power consumption. Preliminary 1-14 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Data Bus Table 1-8 Data Bus Signals Signal Names D0-D15 Signal Type Input/ Output State during Reset Input Signal Description Data bus--These signals provide the bidirectional data bus for external memory accesses. D0-D15 are held in the previous logic state when there is no external bus activity and during hardware reset. This is done with weak "keepers" inside the I/O buffers. Bus Control Table 1-9 Bus Control Signals Signal Name R/W Signal Type Output State during Reset Driven high Signal Description Read/write--This signal indicates the bus access type. A high signal indicates a bus read. A low signal indicates a write to the bus. When accessing memory it can also be used as write enable (WE) signal. When accessing a peripheral chip, the signal acts as a read/write. Enable byte 0--When driven low, this signal indicates access to data byte 0 (D8-D15) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing 16-bit wide SRAM. Enable byte 1--When driven low, this signal indicates access to data byte 1 (D0-D7) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing 16-bit wide SRAM. Bus select--When driven low, this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read. EB0 Output Driven high EB1 Output Driven high OE Output Driven high Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-15 Pin and Signal Descriptions DSP56651 Signal Description Chip Selects Table 1-10 Chip Select Signals Signal Type Output State during Reset Chipdriven Signal Name CS0 Signal Description Chip select 0--This signal is asserted low based on the decode of the internal address bus bits A[31:24] and is typically used as the external flash memory chip select. After reset, accesses using this CS have a default of 15 wait states. Chip select 1-chip select 4--These signals are asserted low based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as chip select signals, these signals become general purpose outputs (GPOs). After reset, these signals are GPOs that are driven high. CS1-CS4 Output Driven high CS5 Output Driven low Chip select 5--This signal is asserted high based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as a chip select signal, this signal becomes a GPO. After reset, this signal is a GPO that is driven low. Preliminary 1-16 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Reset, Mode, and Multiplexer Control Table 1-11 Reset, Mode, and Multiplexer Control Signals Signal Type Input State during Reset Input Signal Name RESET_IN Signal Description Reset input--This signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles. This pin has a 47k pull-up resistor. Note: If MUX_CTL is held high, the RTS signal of the serial data port (UART) becomes the RESET_IN input line. (See Table 1-15 on page 1-26.) Reset output--This signal is asserted low for at least seven CKIL clock cycles under one of the following conditions: * RESET_IN is pulled low for at least three CKIL clock cycles * The alternate RESET_IN signal is enabled by MUX_CTL and is pulled low for at least three CKIL clock cycles * The watchdog count expires This signal is asserted immediately after the qualifier detects a valid RESET_IN signal, remains asserted during RESET_IN assertion, and is stretched for at least seven more CKIL clock cycles after RESET_IN is deasserted. Three CKIL clock cycles before RESET_OUT is deasserted, the MCU boot mode is latched from the MOD signal. Mode select--This signal selects the MCU boot mode during hardware reset. If MOD is driven low at least four CKIL clock cycles before RESET_OUT is deasserted, then the internal MCU ROM ignores the first access and the M*CORE fetches the first word from the first location the external flash memory. If MOD is driven high four CKIL clock cycles before RESET_OUT deassertion, then the internal MCU ROM is enabled and the M*CORE fetches the first word from the first location in the internal ROM. RESET_OUT Output Pulled low MOD Input Input Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-17 Pin and Signal Descriptions DSP56651 Signal Description Table 1-11 Reset, Mode, and Multiplexer Control Signals (Continued) Signal Type Input State during Reset Input Signal Name MUX_CTL Signal Description Multiplexer control--This input allows the designer to select an alternate set of pins to be used for RESET_IN, the debug control port signals, and the JTAG signals as defined below: Normal Alternate (MUX_CTL low) (MUX_CTL high) TRST Interrupt signals INT6/STDA/DSR (See Table 1-12) INT7/SRDA/DTR/SCLK TMS Keypad signals ROW6/SC2A/DCD DSP_DE (See Table 1-14 ROW7/SCKA/RI TCK on page 1-22) TDO Serial Data Port TxD TDI (UART) signals RxD/IC1 (See Table 1-15 RTS/IC2A RESET_IN on page 1-26) CTS MCU_DE If MUX_CTL is driven low, the normal functions are selected. If MUX_CTL is driven high, the alternate functions are selection. Note: The user is responsible to ensure that transition between normal and alternate functions are made smoothly. No provisions are made in the on-chip hardware to assure such a smooth switch. The external command converter uses to drive this signal must ensure that critical pins (such as the JTAG TMS and TRST signals and RESET_IN) are driven with inactive values during and after the switch. The MUX_CTL signal has an internal 100 k pull-down resistor. STO Output Chip driven Soft turn off--This is a general purpose output pin. Its logic state is not affected by reset. For Reset, mode, and MUX control signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary 1-18 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Interrupts Table 1-12 Interrupt Signals Signal Name INT0-INT3 Signal Type State during Reset Signal Description Interrupt 0-interrupt 3--These signals can be programmed as interrupt inputs or GPIO signals. The signals have on-chip 100 k pull-up resistors. As Schmitt trigger interrupt inputs the signals can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. The signals are GPIOs when not programmed as interrupts. After reset, the default state for these signals is general purpose input (GPI). Input or Input Output INT4-INT5 Input or Input Output Interrupt 4-interrupt 5--These signals can be programmed as interrupt inputs or GPIO signals, and have 10-27k pull-up resistors. As Schmitt trigger interrupt inputs, the signals can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. The signals are GPIOs when not programmed as interrupts. After reset, the default state for these signals is GPI. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-19 Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name Normal: INT6 Input or Input Output Signal Type State during Reset Signal Description MUX_CTL driven low Interrupt 6--When selected, this signal can be programmed as an interrupt input or a GPIO signal, and has a 47k pull-up resistor. As a Schmitt trigger interrupt input, the signal can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. STDA Output Audio codec serial transmit data (alternate)--When programmed as STDA, this signal transmits data from the serial transmit shift register in the serial audio codec port. Note: When this signal is used as STDA, the primary STDA signal is disabled. (See Table 1-18 on page 1-31.) DSR Output Data set ready--When programmed as GPIO output, this signal can be used as the DSR output for the serial data port. (See Table 1-15 on page 1-26) The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. Alternate: TRST Input Input MUX_CTL driven high Test Reset--When selected, this signal acts as the TRST input for the JTAG TAP controller. The signal is a Schmitt trigger input that asynchronously initializes the JTAG test controller when asserted. Note: When this signal is enabled, the primary TRST signal is disconnected from the TAP controller. (See Table 1-22.) Preliminary 1-20 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name Normal: INT7 Input or Input Output Signal Type State during Reset Signal Description MUX_CTL driven low Interrupt 7--When selected, this signal can be programmed as an interrupt input or a GPIO signal, and has a 47k pull-up resistor. As a Schmitt trigger interrupt input, the signal can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. SRDA Input Audio codec serial receive data (alternate)--When programmed as SRDA, this signal receives data into the serial receive shift register in the serial audio codec port. Note: When this signal is used as SRDA, the primary SRDA signal is disabled. (See Table 1-18 on page 1-31.) DTR Input Data terminal ready--When programmed as GPIO, this signal is used as the DTR positive and negative edge-triggered interrupt input for the serial data port. (See Table 1-15 on page 1-26.) Serial clock-When so programmed, this signal provides the input clock for the serial data port (UART). (See Table 1-15 on page 1-26.) The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. SCLK Input Alternate: TMS Input Input MUX_CTL driven high Test mode select--When selected, this signal acts as the TMS input for the JTAG TAP controller. The signal is used to sequence that TAP controller state machine. The TMS is sampled on the rising edge of TCK. Note: When this signal is enabled, the primary TMS signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-21 Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name DSP_IRQ Signal Type Input State during Reset Input Signal Description DSP external interrupt request--This active low Schmitt trigger input can be programmed as a level-sensitive or negative edgetriggered maskable interrupt request input during normal instruction processing. If the DSP is in the stop state and DSP_IRQ is asserted, the DSP exits the stop state. This signal has an on-chip 47 k pull-up resistor. For Interrupt signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Timers Table 1-13 Timer Signals Signal Type State during Reset Signal Name TOUT0- TOUT7 Signal Description Timer output 0-7--These are timer output signals. After reset, the default state for these signals is GPI. Note: These signals are GPIOs when not used as timer outputs. Input or Input Output Keypad Port Table 1-14 Keypad Port Signals Signal Type State during Reset Signal Name COL0-COL5 Signal Description Column strobe 0-5--These signals function as keypad column strobes that can be programmed as regular or open-drain outputs. When not used as column strobe signals, these are GPIO signals. After reset, the default state is GPI. Input or Input Output Preliminary 1-22 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Signal Type State during Reset Signal Name COL6 Signal Description Column strobe 6--This signal functions as a keypad column strobe that can be programmed as a regular or open-drain output. MCU timer 1 output compare --When programmed as OC1, this is the MCU Timer 1 output compare signal. When not programmed as OC1 and not used as a column strobe signal, this is a GPIO signal. After reset, the default state is GPI Input or Input Output Output OC1 COL7 Input or Input Output Output Column strobe 7--This signal functions as a keypad column strobe that can be programmed as a regular or open-drain output. Pulse width modulator output--When so programmed, this is the pulse width modulator output. When not programmed as PWM and not used as a column strobe signal, this is a GPIO signal. After reset, the default state is GPI PWM ROW0- ROW4 Input or Input Output Row sense 0-4--These signals function as keypad row senses. When not used as Row Sense signals, these are GPIO signals. After reset, the default state is GPI. These signals have on-chip 22 k pullup resistors. ROW5 Input or Input Output Input Row sense 5--This signal functions as a keypad row sense. IC2B MCU input compare 2 timer--When so programmed, this signal can be the input capture for the MCU input compare 2 timer. When not programmed as IC2B and not used as a row sense signal, this is a GPIO signal. After reset, the default state is GPI. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-23 Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Signal Type State during Reset Signal Name Signal Description Normal: ROW6 Input or Input Output Input or Output MUX_CTL driven low Row sense 6--This signal functions as a keypad row sense and is equipped with an on-chip 100k pull-up resistor. Audio codec serial control 2 (alternate)--When programmed as SC2A, this signal provides I/O frame synchronization for the serial audio codec port. In synchronous mode, the signal provides the frame sync for both the transmitter and receiver. In asynchronous mode, the signal provides the frame sync for the transmitter only. As SC2A, this pin has a 100k pull-down resistor. Note: When this signal is used as SC2A, the primary SC2A signal is disabled. (See Table 1-18 on page 1-31.) Data Carrier Detect--When programmed as GPIO output, this signal can be used as the DSR output for the serial data port. (See Table 1-15 on page 1-26.) After reset, the default state is GPI. MUX_CTL driven high Input Input Digital signal processor debug event--As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode. When programmed as DSP_DE, this signal has an open-drain 100k pull-up. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles. Note: When this signal is enabled, the primary DSP_DE signal is disabled. (See Table 1-21 on page 1-35.) SC2A DCD Output Alternate: DSP_DE Output Preliminary 1-24 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Signal Type State during Reset Signal Name Signal Description Normal: ROW7 Input or Input Output Input MUX_CTL driven low Row sense 7--This signal functions as a keypad row sense. Audio codec serial clock (alternate)--When programmed as SCKA, this signal provides the serial bit rate clock for the serial audio codec port. In synchronous mode, the signal provides the clock input or output for both the transmitter and receiver. In asynchronous mode, the signal provides the clock for the transmitter only. Note: When this signal is used as SCKA, the primary SCKA signal is disabled. (See Table 1-18 on page 1-31.) SCKA RI Output Ring indicator--When programmed as GPIO output, this signal can be used as the RI output for the serial data port. (See Table 1-15.) After reset, the default state is GPI. Alternate: TCK Input Input MUX_CTL driven high Test clock--When selected, this signal provides the TCK input for the JTAG TAP controller. The signal is used to synchronize the JTAG test logic. This signal is equipped with a 47k pull-up resistor. Note: When this signal is enabled, the primary TCK signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) For keypad port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-25 Pin and Signal Descriptions DSP56651 Signal Description Serial Data Port (UART) Table 1-15 Serial Data Port (UART) Signals Signal Type State during Reset Signal Name Signal Description Normal: TxD Input or Input Output MUX_CTL driven low UART transmit--This signal transmits data from the UART. The signal is a GPIO when not programmed as the TxD signal. After reset, the default state for this signal is GPI. Alternate: TDO Output MUX_CTL driven high Test data output--When selected, this signal provides the TDO serial output for test instructions and data from the JTAG TAP controller. TDO is a tri-state signal that is actively driven in the shift-IR and shift-DR controller states. Note: When this signal is enabled, the primary TDO signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) MUX_CTL driven low Input or Input Output Input UART receive--This signal receives data into the UART. Normal: RxD IC1 Input compare 1--When so programmed, the signal connects to an input capture/output compare timer used for autobaud mode support. The signal is a GPIO when not programmed as one of the above functions. This signal has an on-chip 47 k pull-up resistor. After reset, the default state for this signal is GPI. Alternate: TDI Input Input MUX_CTL driven high Test data in--When selected, this signal provides the TDI serial input for test instructions and data for the JTAG TAP controller. TDI is sampled on the rising edge of TCK. Note: When this signal is enabled, the primary TDI signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) Preliminary 1-26 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Table 1-15 Serial Data Port (UART) Signals (Continued) Signal Type State during Reset Signal Name Signal Description Normal: RTS Input or Input Output Input MUX_CTL driven low Request to send--This signal functions as the UART RTS signal. IC2A Input compare 2 A--When so programmed, this signal connects to an input capture timer channel. The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. Alternate: RESET_IN Input Input MUX_CTL driven high Reset input--This signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles. Note: When this signal is enabled, the primary RESET_IN signal is disabled. (See Table 1-11 on page 1-17.) Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-27 Pin and Signal Descriptions DSP56651 Signal Description Table 1-15 Serial Data Port (UART) Signals (Continued) Signal Type State during Reset Signal Name Signal Description Normal: CTS Input or Input Output MUX_CTL driven low Clear to send--This signal functions as the UART CTS signal, and is equipped with a 47k pull-up. After reset, the default state for this signal is GPI. Note: The signal is a GPIO when not used as CTS. MUX_CTL driven high Input Input Microcontroller debug event--As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the MCU has entered the debug mode. The signal is equipped with an open-drain 47k pull-up resistor. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts MCU_DE as an output signal for several clock cycles. Note: When this signal is enabled, the primary MCU_DE signal is disabled. (See Table 1-21.) Alternate: MCU_DE Output Note: * * * * There are four additional signals that support UART operation, provided as follows: DSR--data set ready. This is an alternate function for the INT6 signal. (See Table 1-12 on page 1-19.) DTR--data terminal ready. This is an alternate function for the INT7 signal. (See Table 1-12 on page 1-19.) DCD--data carrier detect. This is an alternate function for the ROW6 signal. (See Table 1-14 on page 1-22.) RI--ring indicator. This is an alternate function for the ROW7 signal. (See Table 1-14 on page 1-22.) For serial data port (UART) signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary 1-28 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Serial Control Port Table 1-16 Serial Control Port Signals Signal Type Output State during Reset Input Signal Name SPICS0- SPICS3 Signal Description Synchronous peripheral chip select 0-3--The output signals provide chip select signals for the queued serial peripheral interface (QSPI). The signals are programmable as active high or active low. Each signal has an on-chip 100 k pull-up resistor. These are GPIO signals when the chip select functions are not being used. After reset, the default state for each signal is GPI. Input or Output SPICS4 Output Input Synchronous peripheral chip select 4--This output signal provides a chip select signal for the QSPI. This signal is programmable as active high or active low. This signal has an on-chip 100 k pulldown resistor. This is a GPIO signal when the chip select function is not being used. After reset, the default state is GPI. Input or Output SCK Output Input Serial clock -- This output signal provides the serial clock from the QSPI for the accessed peripherals. There is a programmable number of clock cycles delay between the assertion of the chip select signal and the first transmission of the serial clock. The polarity and phase of SCK are programmable. This is a GPIO signal when the SCK function is not being used. After reset, the default state is GPI. Input or Output MISO Input Input Synchronous master in slave out--This input signal provides serial data input to the QSPI. Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM MSB or LSB first. This is a GPIO signal when the function is not being used. After reset, the default state is GPI. Input or Output MOSI Output Input Synchronous master out slave in--This output signal provides serial data from the QSPI. Output data can be sampled on the rising or falling edge of SCK and transmitted MSB or LSB first. This is a GPIO signal when the function is not being used. After reset, the default state is GPI. Input or Output For serial control port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-29 Pin and Signal Descriptions DSP56651 Signal Description Smart Card Port After rest, the default state of all Smart Card port pins is GPI. For Smart Card port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-17 Smart Card Port Signals Signal Type Output State during Reset Input Signal Name SIMCLK Signal Description SIM clock--This signal is an output clock from the Smart Card port to the Smart Card. This signal is a GPIO signal when the Smart Card Port is not being used. Input or Output SENSE Input Input SIM sense--This signal is a Schmitt trigger input that signals when a Smart Card is inserted or removed. This signal is a GPIO signal when the Smart Card port is not being used. The signal has an on-chip 100 k pull-down resistor. Input or Output SIMDATA Input/ Output Input SIM data--This bidirectional signal is used to transmit data to and receive data from the Smart Card. In the output state, the signal is open-drain. This signal is a GPIO signal when the Smart Card port is not being used. The signal has an on-chip 47 k pull-up resistor. Input or Output SIMRESET Output Input SIM reset--This signal is an output reset signal from the Smart Card port to the Smart Card. The Smart Card port can activate the reset of an attached Smart Card by driving SIMRESET low. This signal is a GPIO signal when the Smart Card port is not being used. Input or Output PWR_EN Output Input SIM power enable--This active high output enables the external device that supplies VCC to the Smart Card. If this pin is driven high, the external device supplies power to the Smart Card. Driving the signal low cuts off power to card. This permits effective power management and power sequencing for Smart Card enable/disable. This signal is a GPIO signal when the Smart Card port is not being used. This signal has an on-chip 100 k pull-down resistor. Input or Output Preliminary 1-30 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Serial Audio Codec Port After reset, the default state of all serial audio codec pins is Hi-Z. For serial audio codec port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-18 Serial Audio Codec Port Signals Signal Type State during Reset Signal Name STDA Signal Description Audio codec transmit data-- This output signal transmits serial data from the audio codec serial transmitter shift register. It is equipped with a 100k pull-up resistor. This is a GPIO signal when STDA is not being used. Note: This signal is disabled if the alternate STDA function on INT6 is selected. (See Table 1-12 on page 1-19.) Input or Input Output SRDA Input or Input Output Audio codec receive data -- This input signal receives serial data and transfers the data to the audio codec receive shift register. It is equipped with a 100k pull-down resistor. This is a GPIO signal when SRDA is not being used. Note: This signal is disabled if the alternate SRDA function on INT7 is selected. (See Table 1-12 on page 1-19.) SCKA Input or Input Output Audio codec serial clock -- This bidirectional signal provides the serial bit rate clock when only one clock is being used or the TxD clock otherwise. It is equipped with a 100k pull-down resistor. This is a GPIO signal when the serial audio codec port is not being used. Note: This signal is disabled if the alternate SCKA function on ROW7 is selected. (See Table 1-14 on page 1-22.) SC0A Input or Input Output Audio codec serial clock 0--This signal's function is determined by the SCLK mode. * Synchronous mode--serial I/O flag 0 * Asynchronous mode--receive clock I/O This is a GPIO signal when SC0A is not being used. SC1A Input or Input Output Audio codec serial clock 1--This signal's function is determined by the SCLK mode. * Synchronous mode--serial I/O flag 0 * Asynchronous mode--receiver frame sync I/O This is a GPIO signal when SC1A is not being used. Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-31 Pin and Signal Descriptions DSP56651 Signal Description Table 1-18 Serial Audio Codec Port Signals (Continued) Signal Type State during Reset Signal Name SC2A Signal Description Audio codec serial clock 2--This signal's function is determined by the SCLK mode. * Synchronous mode--transmitter and receiver frame sync I/O * Asynchronous mode--transmitter frame sync I/O It is equipped with a 100k pull-down resistor. This is a GPIO signal when SC2A is not being used. Note: This signal is disabled if the alternate SC2A function on ROW6 is selected. (See Table 1-14 on page 1-22.) Input or Input Output Baseband Codec Port After reset, the default state of the baseband codec port pins is Hi-Z. For baseband codec port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-19 Baseband Codec Port Signals Signal Type Output State during Reset Input Signal Name STDB Signal Description Baseband codec transmit data-- This output signal transmits serial data from the baseband codec serial transmitter shift register. This signal is equipped with a 100 pull-up resistor. This is a GPIO signal when STDB is not being used. Input or Output SRDB Input Input Baseband codec receive data -- This input signal receives serial data and transfers the data to the baseband codec receive shift register. This signal is equipped with a 100k pull-down resistor. This is a GPIO signal when SRDB is not being used. Baseband codec serial clock -- This bidirectional signal provides the serial bit rate clock when only one clock is being used or the TxD clock otherwise. This signal is equipped with a 100k pull-down resistor. This is a GPIO signal when the serial baseband codec port is not being used. Input or Output SCKB Input or Input Output Preliminary 1-32 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Table 1-19 Baseband Codec Port Signals (Continued) Signal Type State during Reset Signal Name SC0B Signal Description Baseband codec serial clock 0--This signal's function is determined by the SCLK mode. * Synchronous mode--serial I/O flag 0 * Asynchronous mode--receive clock I/O This signal is equipped with a 100k pull-down resistor. This is a GPIO signal when SC0B is not being used. Baseband codec serial clock 1--This signal's function is determined by the SCLK mode. * Synchronous mode--serial I/O flag 0 * Asynchronous mode--receiver frame sync I/O This signal is equipped with a 100Kk pull-down resistor. This is a GPIO signal when SC1B is not being used. Baseband codec serial clock 2--This signal's function is determined by the SCLK mode. * Synchronous mode--transmitter and receiver frame sync I/O * Asynchronous mode--transmitter frame sync I/O This signal is equipped with a 100k pull-down resistor. This is a GPIO signal when SC2B is not being used. Input or Input Output SC1B Input or Input Output SC2B Input or Input Output Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-33 Pin and Signal Descriptions DSP56651 Signal Description Emulation Port After reset, the default state for the emulation port pins is GPI. Table 1-20 Emulation Port Signals Signal Type State during Reset Signal Name SIZ0-SIZ1 Signal Description Data size 0-1--These signals encode the data size for the current MCU access. When not programmed as data size signals, these are GPIO signals. The signals have on-chip 100 k pull-up resistors. Input or Input Output PSTAT0- PSTAT3 Input or Input Output Pipeline state 0-3--These signals encode the internal MCU execution unit status. When not programmed as pipeline state signals, these are GPIO signals. The signals have on-chip 100 k pull-up resistors. Preliminary 1-34 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Debug Port Control If the MUX_CTL signal is driven high, the alternate MCU_DE and DSP_DE signal locations are selected, and this interface is disabled. For debug port control signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output Table 1-21 Debug Port Control Signals Signal Type Input State during Reset Input Signal Name MCU_DE Signal Description Microcontroller debug event--As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the MCU has entered the debug mode. This signal is equipped with an open-drain 47k pull-up resistor. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts MCU_DE as an output signal for three clock cycles. Output DSP_DE Input Input Digital signal processor debug event--As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode.This signal is equipped with an open-drain 4k K pull-up resistor. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles. Output Preliminary MOTOROLA DSP56651 Technical Data Sheet 1-35 Pin and Signal Descriptions DSP56651 Signal Description JTAG Port When the bottom connector pins are selected as a debug port by holding the MUX_CTL pin at a logic high, the dedicated JTAG pins become inactive. That is, they are disconnected from the JTAG TAP controller. For JTAG signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-22 JTAG Port Signals Signal Type Input State during Reset Input Signal Name TMS Signal Description Test mode select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal 47 k pull-up resistor. MUX_CTL high: INT7 is connected to the JTAG TAP controller and functions as TMS, see Table 1-12 on page 1-19.) Test data input--TDI is a serial test data input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal 47 k pull-up resistor. MUX_CTL high: RxD is connected to the JTAG TAP controller and functions as TDI, see Table 1-15 on page 1-26.) Test data output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. MUX_CTL high: TxD is connected to the JTAG TAP controller and functions as TDO, see Table 1-15 on page 1-26.) Test clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal 47 k pull-up resistor. MUX_CTL high: ROW7 is connected to the JTAG TAP controller and functions as TCK, see Table 1-14 on page 1-22.) Test reset--TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal 47 k pull-up resistor. MUX_CTL high: INT6 is connected to the JTAG TAP controller and functions as TRST, see Table 1-12 on page 1-19.) Factory test mode--Selects factory test mode. Reserved. This pin MUST be connected to ground. TDI Input Input TDO Output Tristated TCK Input Input TRST Input Input TEST Input Input Preliminary 1-36 DSP56651 Technical Data Sheet MOTOROLA SECTION 2 SPECIFICATIONS GENERAL CHARACTERISTICS The DSP56651 is fabricated in high-density CMOS. The DSP56651 specifications are preliminary from design simulations and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-1 Specifications Thermal characteristics Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Internal supply voltage External supply voltage Operating temperature range Storage temperature Symbol VCCI VCCE TA TSTG Value -0.3 to +2.75 -0.3 to +3.6 -40 to +85 -55 to +125 Unit V V C C THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: 1. Symbol RJA or JA RJC or JC JT BGA Value3 TBD TBD TBD Unit C/W C/W C/W 2. 3. Junction-to-ambient thermal resistance is based on measurements on a horizontalsingle-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. These are measured values; testing is not complete. Values were measured on a nonstandard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration. Preliminary 2-2 DSP56651 Technical Data Sheet MOTOROLA Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Internal supply voltage External supply voltage I/O predriver supply voltage Input high voltage Input low voltage Input leakage current Output high voltage (IOH = -400 A) Output low voltage (IOL = 800 A) Total stop mode (DSP and MCU stopped, PLL powered down, timers disabled) DSP run current at 58.8 MHz (MCU stopped, timers disabled, DSP running algorithm from internal memory, BBP and SAP active) PLL supply current (16.8 MHz input, DSP freq = 58.8 MHz, MCU clock = 16.8 MHz) DSP wait current at 58.8 MHz (MCU stopped, timers disabled, BBP and SAP active) Symbol VCCI VCCE VCCHQ VIH VIL IIN VOH VOL ICC_STOP ICCDSP_RUN ICC_PLL ICC_DSP_WAIT Min 2.3 VCCI VCCE 0.7 x VCCE -0.3 -10 0.75 x VCCE 0 -- -- -- -- -- Typ -- -- -- -- -- -- -- -- 60 35 1.6 4.5 9 Max 2.5 3.4 3.4 VCCE + 0.2 0.2 x VCCE 10 VCCE 0.18 x VCCE -- -- -- -- -- Units V V V V V A V V A mA mA mA mA MCU run current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals ICC_MCU_RUN active) MCU doze current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals active) MCU wait current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals active) Timer current (MCU and DSP stopped; 16.8 MHz to timer) Input capacitance per pin Pull-up resistor Note: 1. ICC_MCU_DOZE -- 3 -- mA ICC_MCU_WAIT ICC_TIMER CIN -- -- -- -- 50% 3 500 -- 100% -- -- TBD 180% mA A pF -- value1 Applies to 22 K and 47 K resistors. Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-3 Specifications Clock Requirements CLOCK REQUIREMENTS Table 2-4 Clock Requirements Characteristics CKIH input frequency CKIL input frequency MCU internal frequency DSP internal frequency CKIH input amplitude CKIL input low voltage CKIL input high voltage CKIH input impedance Symbol f1 f2 fMCU-CLK fDSP-CLK VI-CKIH VIL-CKIL VIH-CKIL RI-CKIH Min 0 0 0 -- 500 -0.3 VCCI High TBD Typ -- 32.768 -- -- -- -- -- -- Max 16.8 f1 16.8 58.8 -- 0.2xVCCE 2.77 -- Units MHz kHz MHz MHz mVPP V V M EXTERNAL BUS INTERFACE REQUIREMENTS When the MCU is operating at 16.8 MHz, the bus interface can access 100 ns access time external memory with one wait state or 15 ns access time external memory with no wait states. AC ELECTRICAL CHARACTERISTICS The characteristics listed in this section are given for VDDI = 2.4 V and VDDE = 3.3 V with a capacitive load of 50 pF. Preliminary 2-4 DSP56651 Technical Data Sheet MOTOROLA Specifications Internal Clocks INTERNAL CLOCKS For each occurrence of TDH, TDL, TDC, or IDCYC, substitute with the numbers in Table 2-6. DF, MF, and PDF are the DSP PLL division, multiplication, and predivision factors set in registers. Table 2-5 DSP Clocks Characteristics DSP PLL input frequency DSP PLL input clock cycle time * with PLL disabled * with PLL enabled Symbol EfD ETDC Min 0 59.5 59.5 Max 16.8 273100 Unit MHz ns ns Table 2-6 Internal DSP Clocks Characteristics Internal DSP operation frequency with PLL enabled Internal DSP operation frequency with PLL disabled Internal DSP clock high period * with PLL disabled * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal clock low period * with PLL disabled * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal clock cycle time with PLL enabled Internal clock cycle time with PLL disabled DSP instruction cycle time TDC TDC IDCYC Symbol fD fD Expression (EfD x MF) / (PDF x DF) EfD/2 TDH ETDC (Min) 0.49 x ETDC x PDF x DF/MF (Max) 0.51 x ETDC x PDF x DF/MF (Min) 0.47 x ETDC x PDF x DF/MF (Max) 0.53 x ETDC x PDF x DF/MF ETDC (Min) 0.49 x ETDC x PDF x DF/MF (Max) 0.51 x ETDC x PDF x DF/MF (Min) 0.47 x ETDC x PDF x DF/MF (Max) 0.53 x ETDC x PDF x DF/MF ETDC x PDF x DF/MF 2 x ETDC TDC TDL Table 2-7 MCU Clocks Characteristics Frequency of the internal MCU-CLK clock Internal MCU-CLK clock cycle time Symbol fM TMC Min 0 59.5 Max 16.8 Unit MHz ns Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-5 Specifications Phase-Locked Loop (PLL) Characteristics PHASE-LOCKED LOOP (PLL) CHARACTERISTICS Table 2-8 Phase-Locked Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled1 Expression MF x EfD x 2 / PDF Min 30 Max 120 Unit MHz PLL external capacitor (PCAP pin to VCCP) * MF 4 CPCAP 2 * Notes: (680 * MF-120) recommended (580 * MF-100) minimum (780 * MF-140) maximum pF (1100 * MF) recommended (830 * MF) minimum (1470 * MF) maximum MF > 4 1. 2. The VCO output is further divided by 2 when PLL is enabled. If the division factor (DF) is 1, the operating frequency is VCO . -----------2 CPCAP is the value of the PLL capacitor (connected between PCAP pin and VCCP). (The recommended value for Cpcap is (680 x MF - 120) pF for MF 4 and (1100 x MF) pF for MF > 4.) RESET, MODE SELECT, AND INTERRUPT TIMING Table 2-9 Reset, Mode Select, and Interrupt Timing MCU @16.8 MHz DSP @58.8 MHz Min 1 2 3 4 5 6 7 8 RESET_IN duration to guarantee reset Delay from RESET_IN assertion to RESET_OUT assertion Duration of RESET_OUT assertion Delay from RESET_IN assertion to all pins at Reset Value (periodically sampled and not 100% tested) MOD select setup time MOD select hold time Minimum edge-triggered DSP_IRQ assertion width Minimum edge-triggered DSP_IRQ deassertion width 3 x TCKIL + 0.05 min: 4.5 x TCKIL max: 5.5 x TCKIL 7 x TCKIL min: 4.5 x TCKIL max: 5.5 x TCKIL 3.5 x TCKIL + 0.02 -- -- -- 91.6 137.33 167.85 213.62 137.33 167.85 107 0 10 10 -- -- -- -- -- s s s s ns ns ns Max -- s s Num Characteristics Expression Unit Preliminary 2-6 DSP56651 Technical Data Sheet MOTOROLA Specifications RESET, Mode Select, and Interrupt Timing Table 2-9 Reset, Mode Select, and Interrupt Timing (Continued) MCU @16.8 MHz DSP @58.8 MHz Min 9 10 Minimum edge-triggered INTn width high Minimum edge-triggered INTn width low -- -- TBD TBD Max -- -- ns ns Num Characteristics Expression Unit RESET_IN 1 RESET_OUT All Pins 2 4 3 Reset Value AA1679 Figure 2-1 Reset Timing RESET_OUT 5 6 MOD AA1680 Figure 2-2 Operating Mode Select Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-7 Specifications RESET, Mode Select, and Interrupt Timing DSP_IRQ 7 DSP_IRQ 8 AA1681 Figure 2-3 DSP External Interrupt Timing (Negative Edge-Triggered) INTn 9 INTn 10 AA1682 Figure 2-4 INT0-INT7 External Interrupt Timing Preliminary 2-8 DSP56651 Technical Data Sheet MOTOROLA Specifications External Interface Module (EIM) Timing EXTERNAL INTERFACE MODULE (EIM) TIMING The EIM provides the bus interface between the DSP56651 and external memory and peripherals. It uses the external address bus, data bus, bus control signals, and the chip select signals. Table 2-10 EIM External Bus Output AC Timing Specifications1 MCU @16.8 MHz Num 11 12 13 14 15 16 17 Characteristics Min MCU_CLK rise to address and R/W valid2 MCU_CLK rise to address and R/W invalid (output hold) MCU_CLK rise to CS asserted MCU_CLK rise to CS deasserted (output hold) MCU_CLK fall to OE, EB asserted (read, OEA = 0), EB asserted (write)3 MCU_CLK rise to OE, EB asserted (read, OEA = 1)3 MCU_CLK rise to OE, EB deasserted (output hold) (read)3 -- 0 -- 0 -- -- 0 0 0 -- 0)3 0 15 0 -- 0 -- -- 0 -- Max 4 -- 4 -- 4 4 -- -- -- 4 -- -- -- 4 -- 4 6 -- 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit MCU_CLK rise to EB deasserted (output hold) (write, WEN = 0) 18 19 20 21 22 23 24 25 26 27 28 Note: MCU_CLK fall to EB deasserted (output hold) (write, WEN = 1) MCU_CLK fall to OE, EB asserted (WSC = 0)3 MCU_CLK rise to OE, EB deasserted (output hold) (WSC = Data-in valid to MCU_CLK rise (setup) MCU_CLK rise to data-in invalid (hold) MCU_CLK rise to data-out valid MCU_CLK rise to data-out invalid (output hold) MCU_CLK rise to data-out high impedance MCU_CLK fall to data-out valid (WSC = 0) MCU_CLK rise to data-out invalid (output hold) (WSC = 0) MCU_CLK rise to data-out high impedance (WSC = 0) 1. 2. 3. The following notes apply to this table: * Output timing is measured at the pin. The specifications assume a capacitive load of 50 pF. * R/W, EB, and CS deassertion to address change is 0 ns minimum. * MCU_CLK can be viewed on the CKO pin by programming the clock control register (CKCTL). Address setup to R/W and CS assertion is 0 ns minimum. EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear. Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-9 Specifications External Interface Module (EIM) Timing MCU_CLK 11 ADDRESS R/W 12 CS 13 14 15 OE, EB (OEA=0) (READ) 17 OE, EB (OEA=1) (READ) 16 17 15 EB (WEN=0) (WRITE) 17 EB (WEN=1) (WRITE) 18 OE, EB (WSC=0) 19 15 20 21 DATA in (READ) 22 23 DATA out (WRITE) 24 26 DATA out (WSC=0) (WRITE) 27 AA1683 25 28 Figure 2-5 EIM Read/Write Timing Preliminary 2-10 DSP56651 Technical Data Sheet MOTOROLA Specifications Smart Card Timing SMART CARD TIMING Table 2-11 Smart Card Port to Smart Card AC Timing CKIH @16.8 MHz Num 31 32 33 34 35 Note: Characteristics Min SIMRESET low to SIMCLK low SIMCLK deactivated to SIMDATA tri-state to low SIMDATA low to PWR_EN low SIMRESET low SENSE high to SIMRESET low 1.18 1.18 1.18 40000/f 57 Max 200/f 200/f 200/f -- 76 s s s ns s Unit "f" is CKIH/4 (for 5 V sims) or CKIH/5 (for 3 V sims), as programmed in the Smart Card port. SENSE 35 34 SIMRESET 31 SIMCLK 32 38 SIMDATA 33 PWR_EN AA1684 Figure 2-6 Smart Card Interface Power Down AC Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-11 Specifications QSPI Timing QSPI TIMING The QSPI uses the signals in the serial control port to select individual serial peripherals (using the SPI chip select signals) and transfer data between peripherals and the DSP56651. Table 2-12 QSPI Timing MCU_CLK @ 16.8 MHz Min 301 302 303 304 305 306 307 308 309 310 311 Cycle time Clock (SCK) high or low time Chip-select lag time Inter-queue transfer delay Chip-select lead time Data setup time (inputs) Data hold time (inputs) Data valid (after SCK edge) Data hold time (outputs) Rise time Fall time TQCYC TSW TLAG TTD TLEAD TSU THI TV THO TI TF -- -- -- -- -- -- -- -- -- -- -- 1 -- 1 1 1 0 0.5 -- -2 -- -- Max 504 252 128 -- -- 6 -- 10 10 TMC TMC TQCYC TQCYC TQCYC nS TQCYC nS nS nS nS Num Characteristics Symbol Expression Unit 303 PCS [4:0] 310 SCK (CSPOL = 0) 304 SCK (CSPOL = 1) 306 MISO MSB IN 308 MOSI MSB OUT DATA 309 DATA LSB OUT 311 LSB IN 307 301 302 304 305 MSB IN MSB OUT AA1685 Figure 2-7 QSPI Timings for CPHA = 0 Preliminary 2-12 DSP56651 Technical Data Sheet MOTOROLA Specifications Audio Serial Codec and Baseband Serial Codec Timing 303 PCS [4:0] 301 SCK (CSPOL = 0) 302 SCK (CSPOL = 1) 302 306 MISO MSB IN 308 MOSI MSB OUT DATA 309 DATA LSB OUT 311 LSB IN 307 310 304 305 MSB IN MSB OUT AA1686 Figure 2-8 QSPI Timings for CPHA = 1 AUDIO SERIAL CODEC AND BASEBAND SERIAL CODEC TIMING The audio serial codec port (also called the serial audio port or SAP) and the baseband serial codec port (also called the baseband port or BBP) have the same timing specifications. The timing table uses the following acronyms to describe the signal parameters: tSSICC TXC (SCKA/SCKB Pin) RXC (SC0A/SC0B or SCKA/SCKB Pin) FST (SC2A/SC2B Pin) FSR (SC1A/SC1B or SC2A/SC2B Pin) i ck x ck i ck a = = = = = = = = BBP/SAP clock cycle time Transmit clock Receive clock Transmit frame sync Receive frame sync Internal clock External Clock Internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) Internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) Bit length Word length Word length relative i ck s = bl = wl = wr = Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-13 Specifications Audio Serial Codec and Baseband Serial Codec Timing Table 2-13 SAP and BBP Timing DSP @ 58.8 MHz Case Min Max 430 431 Clock cycle1 Clock high period for internal clock for external clock Clock low period for internal clock for external clock RXC rising edge to FSR out (bl) high RXC rising edge to FSR out (bl) low RXC rising edge to FSR out (wr) high2 RXC rising edge to FSR out (wr) low2 RXC rising edge to FSR out (wl) high RXC rising edge to FSR out (wl) low Data in setup time before RXC (SCK in synchronous mode) falling edge Data in hold time after RXC falling edge FSR input (bl, wr) high before RXC falling edge2 FSR input (wl) high before RXC falling edge FSR input hold time after RXC falling edge Flags input setup before RXC falling edge Flags input hold time after RXC falling edge tSSICC -- 4 x TDC 3 x TDC 68 51 -- -- -- -- -- -- i ck x ck ick xck ick xck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Num Characteristics Symbol Expression Unit 2 x TDC - 12.2 21.8 1.5 x TDC 25.5 2 x TDC - 12.2 21.8 1.5 x TDC 25.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 23.2 6.1 3.6 1.2 28.0 1.2 28.0 3.6 0.0 0.0 23.2 7.3 0.0 432 -- 433 434 435 436 437 438 439 440 441 442 443 444 445 -- -- -- -- -- -- -- -- -- -- -- -- -- 45.1 x ck 26.8 i ck a 45.1 x ck 26.8 i ck a 47.6 x ck 29.3 i ck a 47.6 x ck 29.3 i ck a 45.9 x ck 25.6 i ck a 45.1 x ck 26.8 i ck a -- -- -- -- -- -- -- -- -- -- -- -- -- -- x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s Preliminary 2-14 DSP56651 Technical Data Sheet MOTOROLA Specifications Audio Serial Codec and Baseband Serial Codec Timing Table 2-13 SAP and BBP Timing (Continued) DSP @ 58.8 MHz Case Min Max 446 447 448 449 450 451 452 454 455 457 458 460 461 462 Note: Num Characteristics Symbol Expression Unit TXC rising edge to FST out (bl) high TXC rising edge to FST out (bl) low TXC rising edge to FST out (wr) high2 TXC rising edge to FST out (wr) low2 TXC rising edge to FST out (wl) high TXC rising edge to FST out (wl) low TXC rising edge to data out enable from high impedance TXC rising edge to data out valid TXC rising edge to data out high impedance3 FST input (bl, wr) setup time before TXC falling edge2 FST input (wl) to data out enable from high impedance3 FST input (wl) setup time before TXC falling edge FST input hold time after TXC falling edge Flag output valid after TXC rising edge 1. 2. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 + 0.5 x TDC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- 2.0 21.0 4.0 0.0 -- -- 35.4 x ck 18.3 i ck 37.8 x ck 20.7 i ck 37.8 x ck 20.7 i ck 40.3 x ck 23.2 i ck 36.6 x ck 19.5 i ck 37.8 x ck 20.7 i ck 37.8 x ck 20.7 i ck 43.5 x ck 25.6 i ck 37.8 x ck 19.5 i ck -- -- 32.9 -- -- -- -- x ck i ck -- x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 39.0 x ck 22.0 i ck 3. For internal clock, external clock cycle is defined by ICYC and BBP/SAP control register. Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested. Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-15 Specifications Audio Serial Codec and Baseband Serial Codec Timing 430 431 TXC (Input/Output) 446 432 FST (Bit) Out 447 FST (Word) Out 450 451 Data Out 455 452 FST (Bit) In First Bit 460 FST (Word) In 461 455 457 Last Bit Flags Out 458 460 461 462 AA1687 Note: In the network mode, output flag transitions can occur at the start of each time slot within the frame. In the normal mode, the output flag state is asserted for the entire frame period. Figure 2-9 BBP and SAP Transmitter Timing Preliminary 2-16 DSP56651 Technical Data Sheet MOTOROLA Specifications Audio Serial Codec and Baseband Serial Codec Timing 430 431 RXC (Input/Output) 432 433 FSR (Bit) Out FSR (Word) Out 434 437 438 Data In 439 FSR (Bit) In 441 FSR (Word) In 443 First Bit 440 Last Bit Flags In 442 443 444 445 AA1688 Figure 2-10 BBP And SAP Receiver Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-17 Specifications JTAG Port Timing JTAG PORT TIMING Table 2-14 JTAG Timing DSP @ 58.8 MHz Num 500 501 502 503 504 505 506 507 508 509 510 511 512 513 Characteristics Expression Min TCK frequency of operation TCK cycle time in crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low 1/(3 x TDC) -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0 Max 19.6 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 501 502 TCK (Input) VIH VM VIL 502 VM 503 503 AA0496 Figure 2-11 Test Clock Input Timing Diagram Preliminary 2-18 DSP56651 Technical Data Sheet MOTOROLA Specifications JTAG Port Timing TCK (Input) VIL 504 VIH 505 Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs Input Data Valid Output Data Valid Output Data Valid AA0497 Figure 2-12 Boundary Scan (JTAG) Timing Diagram TCK (Input) 513 TRST (Input) 512 AA1689 Figure 2-13 TRST Timing Diagram Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-19 Specifications JTAG Port Timing TCK (Input) TDI TMS (Input) VIH VIL 508 509 Input Data Valid 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid Output Data Valid AA0498 Figure 2-14 Test Access Port Timing Diagram Preliminary 2-20 DSP56651 Technical Data Sheet MOTOROLA SECTION PACKAGING PACKAGE INFORMATION 3 This section provides information about the available packages for this product. The DSP56651 is available in a 196-pin plastic ball grid array (PBGA) package. The DSP56651 part (RAM-based DSP program memory) is delivered in a 17-mm (outline) PBGA package having a solder-ball footprint identical to that of the 15 mm PBGA. Compatibility between the footprints of the two packages is maintained to minimize impact to the customer's application board routing, such that the same board can be used for both the DSP56651 and DSP56652. 196 PBGA (GT), 17 x 17 mm, with Footprint of 15-mm PBGA The DSP56651 is offered in the non-JEDEC standard, 17-mm PBGA package. The package is "non-standard" in that the single outermost row of solder balls in the array is removed, leaving a 14 x 14 array (196) of solder balls. This package footprint is identical to that of the JEDEC standard 15 mm (outline) 196 PBGA. The pitch of the solder balls is 1 mm. Refer to the following table and figure for package drawing and dimensions. Preliminary MOTOROLA DSP56651 Technical Data Sheet 3-1 Packaging PBGA Package Dimensions PBGA PACKAGE DIMENSIONS Table 3-1 Dimensions for 196 PBGA (17-mm Outline) MILLIMETERS DIM A A1 A2 A3 b D D1 D2 E E1 E2 e R1 MIN 1.32 0.27 0.30 0.75 0.35 17.00 13.00 TBD 17.00 13.00 TBD 1.00 -- MAX 1.75 0.47 0.40 0.88 0.65 BASIC BASIC 17.00 BASIC BASIC 17.00 BASIC 2.50 Preliminary 3-2 DSP56651 Technical Data Sheet MOTOROLA Packaging PBGA Package Mechanical Drawing PBGA PACKAGE MECHANICAL DRAWING D E E2 2x R R1 A2 D2 4X R R1 D1 13x, e A3 A1 A e/2 P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 196x, b AA1696 E1 e/2 Figure 3-1 DSP56651 Mechanical Drawing Preliminary MOTOROLA DSP56651 Technical Data Sheet 3-3 Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56651 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile: (602) 244-6591 The Mfax automated system requests the following information: * * The receiving facsimile telephone number including area code or country code The caller's personal identification number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - - Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages A total of three documents may be ordered per call. The DSP56651 196-pin PBGA package mechanical drawing is referenced as Case 1128-01 Rev. D. Preliminary 3-4 DSP56651 Technical Data Sheet MOTOROLA SECTION 4 DESIGN CONSIDERATIONS HEAT DISSIPATION An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; Ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the Preliminary MOTOROLA DSP56651 Technical Data Sheet 4-1 Design Considerations Heat Dissipation estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) as determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. * * As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, this value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-2 on page 2-2 of this document contains the package thermal values for this chip. Preliminary 4-2 DSP56651 Technical Data Sheet MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of recommendations to assure correct DSP operation: * * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least four 0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. Use at least a four-layer printed circuit board (PCB) with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the R/W, DSP_IRQ, and INT0-INT7 signals. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the PLL supply pins (both VCC and GND). * * * Preliminary MOTOROLA DSP56651 Technical Data Sheet 4-3 Design Considerations Electrical Design Considerations Preliminary 4-4 DSP56651 Technical Data Sheet MOTOROLA SECTION 5 ORDERING INFORMATION Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 5-1 DSP56651 Ordering Information Part Package Type Pin Count 196 Order Number PC56651GC DSP56651 Plastic ball grid array (PBGA) Preliminary MOTOROLA DSP56651 Technical Data Sheet 5-1 Ordering information Preliminary 5-2 DSP56651 Technical Data Sheet MOTOROLA M*CORE, Mfax, and OnCE are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 (within US) 1 (303) 675-2140 (outside US) 1 (303) 675-2150 (direct FAX) MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-2662928 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office, 141 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo, Japan 81-3-5487-8488 Internet: www.motorola-dsp.com |
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